The use of 3-parity convolution codes for digital tape track error check-correction generally was developed in 1978. 5-parity data erasure recovery by 5 parallel exclusive-or (XOR)-engines generally was developed in 2004.
The 5 parallel independent Random Array of Independent Discs (RAID)-5 kind XOR-engines use a lot of silicon die-area for five dedicated 1 megabyte (MB) first-in first-out (FIFO) buffers and ten Direct Memory Access (DMA)-engines in order to reach better Hard Disk read performances, but the five XOR-engines conflict at the same external memory bus, then they cannot be efficiently utilized. Also, it is not programmable and does not work for more than five erasures. Many RAID5/6 controller chips have four XOR-engines in parallel, but they are idle in most of time waiting for data to be ready by the host central processing units (CPUs), especially in cluster EC usages.